01 · OVERVIEW
Project Overview
ns-3 has long supported Ethernet-based communication, however, it has not previously provided a dedicated Switched Ethernet model. This project introduces a modular Ethernet foundation and extends it into a multi-port switched Ethernet architecture with MAC learning, forwarding, buffering, and pluggable scheduling.
Why a Dedicated Ethernet Model?
The existing CSMA model in ns-3 is designed around a shared-medium communication model. It is well suited for networks where multiple devices contend for access to a common channel. Switched Ethernet follows a different architecture, with independent full-duplex links connecting devices to a multi-port switch. Frames are forwarded based on destination MAC addresses, while the switch manages buffering and scheduling at its ports. A dedicated Switched Ethernet model provides these concepts explicitly, enabling a more direct representation of modern Ethernet networks.
Ethernet Foundation
The Ethernet implementation is divided into separate EthernetChannel, EthernetNetDevice, EthernetMac and EthernetPhy components. This separation allows the individual layers to be developed and extended independently while maintaining clear interfaces between the networking stack, Ethernet MAC, physical layer and link.
The EthernetChannel represents the physical Ethernet link between devices. It models the propagation characteristics of the link and is responsible for delivering frames between connected devices with the configured propagation delay. The channel supports full-duplex Ethernet operation.
The EthernetNetDevice provides the ns-3
NetDevice abstraction and connects the higher
networking stack with the Ethernet implementation. It
provides the interface through which Ethernet devices can
participate in an ns-3 network.
The EthernetMac handles Ethernet frame processing and MAC-level transmission and reception. It also provides Ethernet-specific functionality such as IEEE 802.3x PAUSE-based full-duplex flow control and MAC control frames.
The EthernetPhy represents the physical layer between the MAC and EthernetChannel. It applies the configured link rate and models transmission timing, including the Ethernet inter-frame gap.
Switched Ethernet
On top of this Ethernet foundation, the project introduces a modular Ethernet switch. A switch consists of multiple ports and learns the location of connected devices from their source MAC addresses. Based on the learned forwarding information, frames can be delivered to the appropriate output port or flooded when the destination is unknown.
The switch architecture also introduces explicit buffering and a scheduler abstraction, allowing different packet scheduling policies to be implemented without changing the core forwarding logic.
Fig: Class Diagram
In Summary
The project progresses from a reusable full-duplex Ethernet link model to a multi-port switched Ethernet architecture. It provides the foundations required to model Ethernet devices, switch forwarding, MAC learning, buffering, backpressure and scheduling, while keeping the design modular enough to support future Ethernet extensions.
02 · IMPLEMENTATION
Implementation
The implementation was developed incrementally, beginning with the core Ethernet link and then extending it into a multi-port switch architecture. Each component has a clearly defined responsibility, keeping the overall design modular
Ethernet Flow Control
Implemented full-duplex Ethernet flow control using IEEE 802.3x PAUSE frames. The MAC processes PAUSE control frames and temporarily stops transmission when requested, resuming transmission after the configured pause interval. MAC control frame handling was also added to provide the foundation for Ethernet-specific control operations.
Tx/Rx Queue Management
The Ethernet MAC manages the transmit (Tx) and receive (Rx) queues associated with frame transmission and reception. The Tx queue holds packets waiting to be transmitted, while the Rx queue stores packets received from the PHY before they are delivered to the higher layers or processed by the device.
The receive path uses RxIndication() to signal that a packet is available in the Rx queue. This separates packet reception from delivery to the ns-3 networking stack and allows devices such as switch ports to determine how received packets should be handled.
Ethernet Switch
Extended the Ethernet foundation with a multi-port switch architecture. The switch manages multiple Ethernet ports and implements MAC address learning, forwarding and flooding. Source MAC addresses are learned from incoming frames, allowing subsequent frames to be forwarded directly to the appropriate output port.
The switch maintains buffering for frames waiting for an output port. When an output port cannot currently accept a frame, the frame remains in the switch buffer and can be transmitted when the port becomes available. This provides backpressure from the output side and allows queue and memory limits to influence packet forwarding.
Scheduler Framework
Introduced a modular Ethernet switch scheduler framework to determine the order in which buffered frames are selected for transmission. The forwarding logic is kept independent of the scheduling policy, allowing different algorithms to be introduced without modifying the core switch forwarding mechanism.
The initial implementation includes an FCFS (First-Come, First-Served) scheduler, providing a simple baseline for validating the scheduler interface and switch operation. The framework can be extended with additional scheduling policies as the switch model evolves.
Helpers & Configuration
Added helper classes to simplify the creation and configuration of Ethernet devices, channels, and switched Ethernet topologies. The helpers provide a higher-level interface for configuring the underlying components, making it easier to construct Ethernet networks and experiment with different configurations.
03 · TIMELINE
Project Timeline
Here is the detailed timeline
Understanding the Architecture
Studied the existing ns-3 networking architecture and discussed the requirements, design decisions and implementation approach for the Ethernet module.
Ethernet Foundation
Developed the core full-duplex Ethernet model by implementing EthernetChannel and EthernetNetDevice, followed by separation of the Ethernet MAC and PHY layers. Added EthernetHelper and an Ethernet Ping example for configuration and connectivity testing. Implemented IEEE 802.3x PAUSE-based flow control and MAC control frame feature. Added tests for full-duplex communication, link speed, IFG and flow control along with PCAP tracing for the Ethernet Ping example.
Ethernet Switch
Extended the Ethernet model into a modular switched Ethernet architecture with a Switch object managing multiple ports. Added MAC address learning and lookup, forwarding, along with SwitchHelper and a switched Ethernet Ping example for validation. Implemented a shared switch buffer and modular Switch Scheduler framework with FCFS scheduling. Added switch tests for learning, forwarding, queue limits and switch memory backpressure. Refactored queue management from EthernetNetDevice to EthernetMac.
04 · CONTRIBUTIONS
Merge Requests
The following merge requests contain the major implementation work completed during the project.
| Merge Request | Description | Link | Status |
|---|---|---|---|
| ethernet: (GSoC26) Add EthernetChannel and EthernetNetDevice | The Ethernet foundation including EthernetChannel, EthernetNetDevice, EthernetPHY, EthernetMAC and EthernetHelper along with related unit tests and examples. | !2886 | Under Review |
| ethernet: (GSoC26) Add Switched Ethernet with pluggable scheduler | The Switched Ethernet model with MAC address learning and forwarding, shared switch buffering, a modular Switch Scheduler framework and FCFS scheduling policy. | !2967 | Under Review |
05 · VALIDATION
Tests & Examples
Tests and examples were developed to validate individual Ethernet components as well as complete switched Ethernet communication.
Tests
| Test | Purpose |
|---|---|
| EthernetFullDuplexTestCase | Validates simultaneous transmission and reception over a full-duplex Ethernet link. |
| EthernetInterframeGapTestCase | Validates Ethernet inter-frame gap timing between consecutive frame transmissions. |
| EthernetLinkSpeedTestCase | Validates transmission timing for different Ethernet link speeds and corresponding frame transmission times. |
| EthernetFlowControlTestCase | Validates IEEE 802.3x PAUSE-frame based flow control and pause/resume behavior. |
| SwitchLearningTestCase | Validates MAC address learning and lookup and flooding. |
| EthernetSwitchQueueLimitTestCase | Validates forwarding behavior when the output port queue reaches its configured queue limit. |
| EthernetSwitchMemoryCheckTestCase | Validates that the switch-level memory limit prevents frames from being forwarded when sufficient switch memory is unavailable, even when output port queues have space. |
| EthernetSwitchRxBackpressureTestCase | Validates switch memory backpressure by ensuring that a frame rejected by the switch memory policy remains in the ingress RX queue for later processing. |
| EthernetSwitchFCFSTestCase | Validates first-come, first-served scheduling by ensuring frames are forwarded in the order they are received and that frames that cannot be accepted by the output port are handled according to the FCFS scheduling policy. |
Examples
| Example | Purpose |
|---|---|
| Ethernet Ping | Demonstrates basic two-node communication using EthernetChannel and EthernetNetDevice, including InternetStackHelper and ICMP ping. |
| Switched Ethernet Ping | Demonstrates communication between two end hosts through an Ethernet switch and validates MAC learning, flooding and unicast forwarding. |
06 · NEXT STEPS
Future Enhancements
Additional Scheduling Policies
Extend the switch scheduler with additional scheduling policies such as Weighted Round Robin (WRR), Priority-based scheduling, and other queue scheduling mechanisms.
VLAN Support
Extend the switched Ethernet model to support Virtual LANs (VLANs), including VLAN tagging, port-based VLAN configuration and VLAN-aware frame forwarding.
Spanning Tree Protocol
Add support for the Spanning Tree Protocol (STP) to prevent Layer 2 forwarding loops and enable more realistic Ethernet switch topologies with redundant links.
Advanced Switch Memory Models
Extend the switch memory model to support shared memory pools between queues or across the switch, enabling more realistic buffer allocation and congestion behavior.
07 · ACKNOWLEDGEMENTS
Acknowledgements
I would like to thank my mentors for their continuous guidance, technical feedback and support throughout the project. Grateful to the ns-3 community for providing an open-source environment in which this work could be developed, discussed and reviewed and Google Summer of Code for providing the opportunity.
08 · REFERENCES
References
- Carrier Sense Multiple Access With Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, ANSI/IEEE Std 802.3-1985, 1985, doi: 10.1109/IEEESTD.1985.82837.
- Efficient Gigabit Ethernet Switch Models for Large-scale Simulation, Dong Jin, David M. Nicol, and Matthew Caesar.
- IEEE Standard for Ethernet, IEEE Std 802.3-2022 (Revision of IEEE Std 802.3-2018), pp. 1-7025, 29 July 2022, doi: 10.1109/IEEESTD.2022.9844436.
- IEEE Standard for Local and Metropolitan Area Networks: Media Access Control (MAC) Bridges, IEEE Std 802.1D-2004 (Revision of IEEE Std 802.1D-1998), pp. 1-281, 9 June 2004, doi: 10.1109/IEEESTD.2004.94569.
- ns-3: Network Simulator 3.